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 CA3227
TM
Data Sheet
May 2000
File Number
1345.5
High-Frequency NPN Transistor Array For Low-Power Applications at Frequencies Up to 1.5GHz
The CA3227 consists of five general purpose silicon NPN transistors on a common monolithic substrate. Each of the transistors exhibits a value of fT in excess of 3GHz, making them useful from DC to 1.5GHz. The monolithic construction of these devices provides close electrical and thermal matching of the five transistors.
Features
* Gain-Bandwidth Product (fT) . . . . . . . . . . . . . . . . . >3GHz * Five Transistors on a Common Substrate
Applications
* VHF Amplifiers * VHF Mixers * Multifunction Combinations - RF/Mixer/Oscillator * IF Converter * IF Amplifiers
Ordering Information
PART NUMBER (BRAND) CA3227E CA3227M (3227) CA3227M96 (3227) TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC Tape and Reel PKG. NO. E16.3 M16.15 M16.15
* Sense Amplifiers * Synthesizers * Synchronous Detectors * Cascade Amplifiers
Pinout
CA3227 (PDIP, SOIC) TOP VIEW
1 2 3 4 SUBSTRATE 5 6 7 8 Q3 Q4 Q2 Q5 16 15 14 13 12 11 10 9
Q1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000
CA3227
Absolute Maximum Ratings
Collector to Emitter Voltage (VCEO). . . . . . . . . . . . . . . . . . . . . . . 8V Collector to Base Voltage (VCBO) . . . . . . . . . . . . . . . . . . . . . . . 12V Collector to Substrate Voltage (VCIO, Note 1) . . . . . . . . . . . . . . 20V Collector Current (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) 16 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . 90 16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 185 Maximum Power Dissipation (Any One Transistor) . . . . . . . . 85mW Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. The collector of each transistor of these devices is isolated from the substrate by an integral diode. The substrate (Terminal 5) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
TA = 25oC SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
DC CHARACTERISTICS FOR EACH TRANSISTOR Collector to Base Breakdown Voltage Collector to Emitter Breakdown Voltage V(BR)CBO V(BR)CEO IC = 10A, IE = 0 IC = 1mA, IB = 0 IC1 = 10A, IB = 0, IE = 0 VEB = 4.5V, IC = 0 VCE = 5V, IB = 0 VCB = 8V, IE = 0 VCE = 6V IC = 10mA IC = 1mA IC = 0.1mA Base to Emitter Voltage Collector to Emitter Saturation Voltage Base to Emitter Saturation Voltage NOTE: 3. On small-geometry, high-frequency transistors, it is very good practice never to take the Emitter Base Junction into reverse breakdown. To do so may permanently degrade the hFE. Hence, the use of IEBO rather than V(BR)EBO. These devices are also susceptible to damage by electrostatic discharge and transients in the circuits in which they are used. Moreover, CMOS handling procedures should be employed. VBE VCE SAT VBE SAT VCE = 6V IC = 10mA, IB = 1mA IC = 10mA, IB = 1mA IC = 1mA 12 8 20 40 0.62 0.74 20 10 110 150 150 0.71 0.13 10 1 100 0.82 0.50 0.94 V V V V V V A A nA
Collector to Substrate Breakdown Voltage V(BR)CIO Emitter Cutoff Current (Note 3) Collector Cutoff Current Collector Cutoff Current DC Forward Current Transfer Ratio IEBO ICEO ICBO hFE
2
CA3227
Electrical Specifications
PARAMETER TA = 25oC, 200MHz, Common Emitter, Typical Values Intended Only for Design Guidance SYMBOL TEST CONDITIONS TYPICAL VALUES UNITS
DYNAMIC CHARACTERISTICS FOR EACH TRANSISTOR Input Admittance Y11 b11 g11 Output Admittance Y22 b22 g22 Forward Transfer Admittance Y21 Y21 21 Reverse Transfer Admittance Y12 Y12 12 Input Admittance Y11 b11 g11 Output Admittance Y22 b22 g22 Forward Transfer Admittance Y21 Y21 21 Reverse Transfer Admittance Y12 Y12 12 Small Signal Forward Current Transfer Ratio h21 IC = 1mA, VCE = 5V IC = 10mA, VCE = 5V TYPICAL CAPACITANCE AT 1MHz, THREE-TERMINAL MEASUREMENT Collector to Base Capacitance Collector to Substrate Capacitance Collector to Emitter Capacitance Emitter to Base Capacitance CCB CCI CCE CEB VCB = 6V VCI = 6V VCE = 6V VEB = 3V 0.3 1.6 0.4 0.75 pF pF pF pF IC = 10mA, VCE = 5V IC = 10mA, VCE = 5V IC = 10mA, VCE = 5V IC = 10mA, VCE = 5V IC = 1mA, VCE = 5V IC = 1mA, VCE = 5V IC = 1mA, VCE = 5V IC = 1mA, VCE = 5V 4 0.75 2.7 0.13 29.3 -33 0.38 -97 4.8 2.85 2.75 0.9 95 -62 0.39 -97 7.1 17 mS mS mS mS mS Degrees mS Degrees mS mS mS mS mS Degrees mS Degrees
Spice Model
.model NPN + + + + + + + +
(Spice 2G.6)
BF = 2.610E + 02 RC = 1.000E + 01 IK = 1.000E - 01 ISC = 9.25E - 14 CJS = 1.800E - 12 CJC = 9.100E - 13 AF = 1.000E + 00 MJS = 3.530E - 01
BR = 4.401E + 00 RE = 7.396E - 01 ISE = 1.87E - 14 NC = 1.333E + 00 CJE = 1.010E - 12 PC = 3.850E - 01 EF = 1.000E + 00 RBM = 30.00
IS = 6.930E - 16 VA = 6.300E + 01 NE = 1.653E + 00 TF = 1.775E - 11 PE = 8.350E - 01 MC = 2.740E - 01 FC = 5.000E - 01 RBV = 100
RB = 130.0E + 00 VB = 2.208E + 00 IKR = 1.000E - 02 TR = 1.000E - 09 ME = 4.460E - 01 KF = 0.000E + 00 PJS = 5.410E - 01 IRB = 0.00
Please Note: No measurements have been made to model the reverse AC operation (tr is an estimation).
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CA3227 Typical Performance Curves
160 150 140 130 120 110 100 90 80 70 60 50 40 VCE = 6V, TA = 25oC 30 20 0.1 1.0 IC (mA) 3.5 3.0 2.5 fT (GHz) 2.0 1.5 1.0 0.5 0 VCE = 5V, TA = 25oC
hFE
10
100
0
5 IC (mA)
10
15
FIGURE 1. hFE vs COLLECTOR CURRENT
FIGURE 2. fT vs COLLECTOR CURRENT
RSOURCE = 500, VCE = 6V, TA = 25oC 30 NOISE FIGURE (dB) FREQUENCY = 10Hz NOISE FIGURE (dB) 30
RSOURCE = 1k, VCE = 6V, TA = 25oC FREQUENCY = 10Hz
20
100Hz
20
100Hz
1kHz 10
1kHz 10 10kHz 100kHz 0.01 0.1 IC (mA) 1.0 10.0
10kHz 100kHz 0.01 0.1 IC (mA) 1.0 10.0
FIGURE 3. NOISE FIGURE vs COLLECTOR CURRENT
FIGURE 4. NOISE FIGURE vs COLLECTOR CURRENT
1.75 1.50 CAPACITANCE (pF) 1.25 1.00 0.75 0.50 0.25 0 0 1 2 3 4 5 6 7 8 9 10 BIAS VOLTAGE (V) CCI
CEB CCB
FIGURE 5. CAPACITANCE vs BIAS VOLTAGE
4
CA3227 Die Characteristics
DIE DIMENSIONS: 46 mils x 32 mils
Metallization Mask Layout
CA3227
(14)
(13)
(12)
(11)
(15)
(10)
(16)
(9)
(1)
(8)
(2)
(7)
(3)
(4)
(5) SUBSTRATE
(6)
5
CA3227 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
A
E A2 L A C L
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1
A1 A2
-C-
B B1 C D D1 E
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 16 0.430 0.150
2.54 BSC 7.62 BSC 2.93 16 10.92 3.81
6
CA3227 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574
A1 B C D
A1 0.10(0.004) C
E e H h L N
e
B 0.25(0.010) M C AM BS
0.050 BSC 0.2284 0.0099 0.016 16 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 16 0o 6.20 0.50 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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